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XRD9814/XRD9816
3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors
December 1999-2
FEATURES * 14-Bit (XRD9814) or 16-Bit (XRD9816) A/D Converter * No Missing Codes * Triple-Channel, 2.5 MSPS Color Scan Mode * Single-Channel, 6 MSPS Monochrome Scan Mode * Triple Correlated Double Sampler * Triple 10-Bit Programmable Gain Amplifier * Triple 10-Bit Offset Compensation DAC * Fully Differential or Single-Ended Inputs * CDS or S/H Mode * Inverting or Non-Inverting Mode * Internal Voltage Reference * Serial Control: On Data Bus or Separate Pins GENERAL DESCRIPTION The XRD9814/9816 is a fully integrated, high-performance analog signal processor/digitizer specifically designed for use in 3-channel linear Charge Coupled Device (CCD) and Contact Image Sensitive (CIS) imaging applications. Each channel of the XRD9814/9816 includes a Correlated Double Sampler (CDS), Programmable Gain Amplifier (PGA) and channel offset adjustment. After gain and offset adjustment, the analog inputs are sequentially sampled and digitized by an accurate 14/ 16-bit A/D converter. The analog front-end can be configured for inverting/non-inverting input, CDS or sample-hold (S/H) mode, or AC/DC coupling, making the XRD9814/9816 suitable for use in CCD, CIS and other data acquisition applications. The CDS mode of operation supports both line and pixel-clamp modes and can be used to achieve significant reduction in system 1/f noise and CCD reset clock feed-through. In S/H mode the internal DCrestore voltage clamp can be enabled or disabled to support AC-coupled or DC inputs. Sampling mode, 10-bit PGA gain (1024 linear steps), 8-bit fine offset adjustment (256 linear steps), 2-bit gross offset adjustment and input signal polarity are all programmable through a serial interface. PGA gain range is 1 to 10, and channel offset range is -300mV to 300mV for fine adjustment and additional -400mV to +200mV for gross offset adjustment. The A/D Full-Scale Range (FSR) is programmable to 2V or 3V. * 14-Bit or 8-Bit (Nibble) Parallel Data Output (XRD9814) * 16-Bit or 8-Bit (Nibble) Parallel Data Output (XRD9816) * 5V Operation and 3V I/O Compatibility * Low Power CMOS: 500mW @ 5V APPLICATIONS * * * * * 48-Bit Color Scanners (XRD9816) 42-Bit Color Scanners (XRD9814) CCD or CIS Color Imagers Gray Scale Scanners Film Scanners
ORDERING INFORMATION
Part No. XRD9814ACV XRD9816ACV Package Type 48-Lead TQFP 48-Lead TQFP Temperature Range 0C to +70C 0C to +70C
Rev. 1.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRD9814/9816
BSAMP VSAMP ADCCLK LCLMP
INTERNAL TIMING CONTROL
INSEL 10-BIT RED(+) RED(-) PROGRAMMABLE BUFFERED CDS or S/H PGA I/O CONTROL AND CONFIGURATION REGISTERS OUTSEL SDI SCLK LOAD
REGISTER
AGND1
10-BIT DAC
TEST1 TEST2
REGISTER AVDD1 AVDD2 10-BIT GRN(+) GRN(-) PROGRAMMABLE BUFFERED CDS or S/H PGA 3-1 MUX AVDD3
REGISTER SGND VREF 1.24V OEB AGND2 REGISTER REFIN OUTPUT PORT 14/16-BIT A/D 10-BIT BLU(+) BLU(-) PROGRAMMABLE BUFFERED CDS or S/H PGA CAPP REGISTER CAPN VREF- VREF+ DB<13:0> or DB<15:0>
10-BIT DAC
14/16
10-BIT DAC VCLAMP (Internal) CREF DVDD REGISTER DGND
Figure 1. Block Diagram
Rev. 1.00
2
XRD9814/9816
DGND DVDD LOAD SCLK DB10 DB11 DB12 DB13
PIN CONFIGURATION
DB9
48
47
46
45
44
43
42
41
40
39
38
37
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N/C N/C AVDD3
OUTSEL
OEB
SDI
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
INSEL ADCCLK BSAMP VSAMP LCLMP AVDD1 AGND1 SGND CAPN CAPP CREF TEST2
XRD9814
13
14
15
16
17
18
19
20
21
22
23
24
GRN(+)
GRN(-)
RED(-)
BLU(+)
AGND2
RED(+)
AVDD2
BLU(-)
N/C
N/C
N/C
Note: Pins 17,20 and 23 should be connected to AGND2 to improve noise immunity
PIN DESCRIPTION - XRD9814
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N/C N/C AVDD3 AVDD2 AGND2 RED(+) Description Data Output Bit 8 Data Output Bit 7 Data Output Bit 6 Data Output Bit 5 Data Output Bit 4 Data Output Bit 3 Data Output Bit 2 Data Output Bit 1 Data Output Bit 0 No Connect No Connect Analog Power Supply Analog Power Supply Analog Ground (Substrate) Red Positive Analog Input
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TEST1
XRD9814/9816
PIN DESCRIPTION - XRD9814 (CONT'D)
Pin No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name RED(-) N/C GRN(+) GRN(-) N/C BLU(+) BLU(-) N/C TEST1 TEST2 CREF CAPP CAPN SGND AGND1 AVDD1 LCLMP VSAMP BSAMP ADCCLK INSEL OUTSEL OEB LOAD SDI SCLK DGND DVDD DB13 DB12 DB11 DB10 DB9 Description Red Negative Analog Input No Connect, (Note 5) Green Positive Analog Input Green Negative Analog Input No Connect, (Note 5) Blue Positive Analog Input Blue Negative Analog Input No Connect, (Note 5) Internal Use Only Internal Use Only Decoupling Cap for CDS Reference Decoupling Cap for Positive Reference Decoupling Cap for Negative Reference Substrate Gnd Analog Ground (Substrate) Analog Power Supply Line Clamp Enable Video Level Sampling Clock Black Level Sampling Clock A/D Converter Clock Input Mode Select (Note 1) Output Mode Select (Note 2) Data Output Enable Register Write Enable (Note 5) Serial Data Input (Note 4) Serial Shift Clock (Note 3) Ground (Output Drivers and Internal Decode Logic) Digital Power Supply (Output Drivers and Internal Decode Logic) Data I/O Bit 13 (Note 4) Data I/O Bit 12 (Note 3) Data Output Bit 11 Data Output Bit 10 Data Output Bit 9
Note 1: INSEL=0 --> SCLK, SDI, and LOAD pins are active for serial programming; INSEL=1 --> SCLK and SDI pins are inactive, and the serial programming is done through I/O pins DB12 and DB13 as described in Notes 3~4 with LOAD tri-stating DB12 and DB13. Note 2: OUTSEL=0 --> 14-bit parallel output mode select; OUTSEL=1 --> 8-bit nibble output mode select. Note 3: For INSEL=1, DB12 becomes the SCLK input during serial programming. Note 4: For INSEL=1, DB13 becomes the SDI input during serial programming. Note 5: Pins 17, 20 and 23 may be connected to AGND2 to improve noise immunity.
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4
XRD9814/9816
OUTSEL
37
DGND
PIN CONFIGURATION
DVDD DB11 DB12 DB13 DB14 DB15
LOAD
39
SCLK
48
47
46
45
44
43
42
41
40
38
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AVDD3
OEB
SDI
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31
INSEL ADCCLK BSAMP VSAMP LCLMP AVDD1 AGND1 SGND CAPN CAPP CREF TEST2
XRD9816
30 29 28 27 26 25
13
14
15
16
17
18
19
20
21
22
23
24
RED(-)
GRN(-)
BLU(-)
RED(+)
GRN(+)
AVDD2
AGND2
BLU(+)
N/C
N/C
N/C
Note: Pins 17,20 and 23 should be connected to AGND2 to improve noise immunity
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Name DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AVDD3 AVDD2 AGND2 RED(+)
Description Data Output Bit 10 Data Output Bit9 Data Output Bit 8 Data Output Bit 7 Data Output Bit 6 Data Output Bit 5 Data Output Bit 4 Data Output Bit 3 Data Output Bit 2 Data Output Bit 1 Data Output Bit 0 Analog Power Supply Analog Power Supply Analog Ground (Substrate) Red Positive Analog Input
Rev. 1.00
5
TEST1
XRD9814/9816
Pin Configuration - XRD9816
Pin No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 46 45 47 48 Name RED(-) N/C GRN(+) GRN(-) N/C BLU(+) BLU(-) N/C TEST1 TEST2 CREF CAPP CAPN SGND AGND1 AVDD1 LCLMP VSAMP BSAMP ADCCLK INSEL OUTSEL OEB LOAD SDI SCLK DGND DVDD DB15 DB13 DB14 DB12 DB11 Description Red Negative Analog Input No Connect, (Note 5) Green Positive Analog Input Green Negative Analog Input No Connect, (Note 5) Blue Positive Analog Input Blue Negative Analog Input No Connect, (Note 5) Internal Use Only Internal Use Only Decoupling Cap for CDS Reference Decoupling Cap for Positive Reference Decoupling Cap for Negative Reference Substrate Gnd Analog Ground (Substrate) Analog Power Supply Line Clamp Enable Video Level Sampling Clock Black Level Sampling Clock A/D Converter Clock Input Mode Select (Note 1) Output Mode Select (Note 2) Data Output Enable Register Write Enable (Note 5) Serial Data Input (Note 4) Serial Shift Clock (Note 3) Ground (Output Drivers and Internal Decode Logic) Digital Power Supply (Output Drivers and Internal Decode Logic) Data I/O Bit 15 (Note 4) Data Output Bit 13 Data I/O Bit 14 (Note 3) Data Output Bit 12 Data Output Bit 11
Note 1: INSEL=0 --> SCLK, SDI, and LOAD pins are active for serial programming; INSEL=1 --> SCLK and SDI pins are inactive, and the serial programming is done through I/O pins DB14 and DB15 as described in Notes 3~4 with LOAD tri-stating DB14 and DB15. Note 2: OUTSEL=0 --> 16-bit parallel output mode select; OUTSEL=1 --> 8-bit nibble output mode select. Note 3: For INSEL=1, DB14 becomes the SCLK input during serial programming. Note 4: For INSEL=1, DB15 becomes the SDI input during serial programming. Note 5: Pins 17, 20 and 23 may be connected to AGND2 to improve noise immunity.
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6
XRD9814/9816
ELECTRICAL CHARACTERISTICS AVDD=DVDD=5.0V, ADCCLK=6MHz, Input Range = 2V, Ta=25oC unless otherwise specified
Parameter A/D CONVERTER Resolution Resolution Maximum Conversion Rate Differential Non-Linearity Differential Non-Linearity Monotonicity Monotonicity Input Referred Offset Offset Drift Input Referred Gain Error Gain Error Drift Input Voltage Range 2V Full-Scale Range 3V Full-Scale Range CDS - S/H SPECIFICATIONS Input Voltage Range Input Buffer Disabled (Note 1) Input Buffer Enabled Input Bias Current Input Buffer Disabled (Note 2) Input Buffer Enabled Input Switch On -Resistance Input Switch Off -Resistance Internal Voltage Clamp CCD Input (Inverting) S/H Input (Non-Inverting) Vclamp Vclamp 4.0 0.6 4.2 0.8 4.4 1.0 V V PB2=0, Config Reg #1 PB2=1, Config Reg #1 IBB Ron Roff 100 150 1000 25 250 nA M IB 25 uA Gain=1, PB1=0, Config Reg #1 TA=70o C, PB1=1, Config Reg #1 Clamp Enabled Clamp Disabled INVSRB 0.5 AVDD-1 V INVSR AGND AVDD V Pixel Clamp, PB1=0, Config Reg #1 Line Clamp, PB1=1, Config Reg #1 IVR IVR 0 0 2.0 3.0 V V PB5=0, Config Reg #1 PB5=1, Config Reg #1 R R Fc DNL DNL M M ZSE ZSD FSE FSD 14 16 6 8 +/-0.8 -0.95/+1.2 Yes Yes 40 15 +/- 2 0.003 mV uV/oC % FS % FS oC BITS BITS MSPS LSB LSB XRD9814 XRD9816 XRD9814 XRD9816 XRD9814 XRD9816 Symbol Min Typ Max Unit Conditions
Note 1: ADC digitizing range = (A/D Full-Scale Range/PGA Gain) Note 2: Due to switch capacitor input.
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7
XRD9814/9816
ELECTRICAL CHARACTERISTICS (CONT'D) AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified
Parameter OFFSET SPECIFICATIONS Fine Offset Adjustment Min Fine Offset Adjustment Max Fine Offset Adjustment Step Fine Offset Adjustment Linearity Gross Offset Adjustment Min Gross Offset Adjustment Max OFGR OFGR -360 +360 -400 +200 +200 -440 +440 mV mV mV 2-Bit, 4 Settings OFR OFR OFRES OFRL -270 +270 -300 +300 2.34 +/-1.5% -330 +330 mV mV mV 8-Bit, 256 Settings Symbol Min Typ Max Unit Conditions
Gross Offset Adjustment Step OFGRES PGA SPECIFICATIONS Gain Range Min (Absolute Value) Gain Range Max (Absolute Value) GRAN 8.5 GRAN 1.0
1.10
1.20
V/V
-1 for PB2=0, +1 for PB2=1, Config Reg #1
9.5
10.5
V/V
-10 for PB2=0, +10 for PB2=1, Config Reg#1
Gain Resolution
GRES
0.0083
V/V
10-Bit 1024 Steps
SYSTEM SPECIFICATIONS (Includes CDS, PGA and A/D) Differential Non-Linearity Differential Non-Linearity Integral Non-Linearity Input Referred Noise PGA Gain = -1.63 IRNmin +3.4 LSB XRD9814, 1-Channel CIS Mode, 6MSPS, Low Gain PGA Gain = -5.0 IRNmax +1.1 LSB XRD9814, 1-Channel CIS Mode, 6MSPS, Low Gain System Offset PGA Gain= -1 IRO min +70 mV XRD9814/9816, 3-Channel Mode, 6MSPS XRD9814/9816, 3-Channel Mode, 6MSPS DNL DNL INL -0.9 -0.95 +/-0.8 -0.95/+1.2 +/-10.0 +1.5 +2.0 LSB LSB LSB XRD9814, PGA Gain = 1 XRD9816, PGA Gain = 1 XRD9814, PGA Gain = 1
PGA Gain= -10
IRO max
+70
mV
Rev. 1.00
8
XRD9814/9816
ELECTRICAL CHARACTERISTICS (CONT'D) AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified
Parameter TIMING SPECIFICATIONS ADCCLK Pulse Width BSAMP falling edge delay from rising ADCCLK BSAMP falling edge to VSAMP falling edge. ADCCLK Period (1 Ch. Mode) ADCCLK Period (3 Ch. Mode) 1-Channel Conversion Period 3-Channel Conversion Period BSAMP Pulse Width VSAMP Pulse Width VSAMP falling edge to BSAMP falling edge. VSAMP falling edge delay from rising ADCCLK. VSAMP falling edge delay from rising ADCCLK PGA Settling Time Aperture Delay VSAMP TIMING OPTION #1 VSAMP rising edge delay from falling ADCCLK (Note 1) VSAMP TIMING OPTION #2 VSAMP rising edge delay from rising ADCCLK (Note 1) WRITE SPECIFICATIONS Data Setup Time Data Hold Time Load Setup Time Load Hold Time Load Pulse Width tds tdh tlcs tlch tplw 15 15 15 15 25 ns ns ns ns ns tvrcr 15 ns tvrcf is not required, Config REG # 1, PB0=1 tvrcf 15 ns tvrcr is not required, Config REG #1, PB0=0 tvfcr tvfcr tstl tap 30 70 70 5 ns ns ns ns All modes except 1-Channel S/H 1-Channel S/H, Config REG #1, PB2=1, PB7=1 tcp1 tcp3 tcr1 tcr3 tpwb tpwv tvbf 166 133 166 400 30 30 70 ns ns ns ns ns ns ns tbvf 70 ns taclk tbfcr 66.5 10 ns ns Symbol Min Typ Max Unit Conditions
Note 1: VSAMP Timing Option #2 allows additional timing flexibility by allowing the rising edge of VSAMP to occur approximately one-half ADCCLK period earlier than Option #1. Option #2 is only available in 3-Channel Operation (PB4=0, PB3=0, Configuration Register #1).
Rev. 1.00
9
XRD9814/9816
ELECTRICAL CHARACTERISTICS (CONT'D) AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified
Parameter Symbol Min Typ Max Unit Conditions
DATA READBACK SPECIFICATIONS Address Access Time Output Enable Access Time taa (1) taoe (1) 15 15 ns ns
ADC DIGITAL OUTPUT SPECIFICATIONS Output Delay Tri-State to Data Valid Output Enable High to Tri-State Latency RGB inputs DIGITAL INPUTS Input High Logic Level Input Low Logic Level High Level Input Current Low Level Input Current Input Capacitance DIGITAL OUTPUTS (DVDD=5V) Output High Voltage Output Low Voltage Output Capacitance DIGITAL OUTPUTS (DVDD=3.3V) Output High Voltage Output Low Voltage Output Capacitance POWER SUPPLY Analog Power Supply Digital Power Supply Analog Supply Current Digital Supply Current Stand-By Mode Power AVDD DVDD IDDA IDDD PDoff 4.5 3.0 5.0 5.0 110 2 65 80 5.5 5.5 V V mA mA mW 3CH CDS Mode Digital Output CLoad=30pF, all pins. VOH VOL COUT 10 2.8 0.3 V V pF IL=2ma IL=-2ma VOH VOL COUT 10 4.2 0.4 V V pF IL=2ma IL=-2ma VIH VIL IIH IIL CIN 5 5 10 80 20 % DVDD % DVDD uA uA pF DVDD=3-5V DVDD=3-5V tod tlz thz lat 20 8 8 7 ns ns ns ADCCLK
Note 1: Start of valid data depends on which timing becomes effective last, taoe or taa.
Rev. 1.00
10
XRD9814/9816
Function Configuration Reg #1 Configuration Reg #2 Red Gain Green Gain Blue Gain Red Offset Green Offset Blue Offset A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 PB9-PB0 See Configuration Register #1 See Configuration Register #2 10-Bit Gain 10-Bit Gain 10-Bit Gain 2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment 2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment 2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment
Table 1. XRD9814/9816 Register Overview
A2 A1 A0 Address 0 0 0
Bit Assignment PB9 Single Channel Power Save Mode PB8 Digital Reset PB7 PB6 Clamp Mode 0 1 0 1 00 01 10 11 0 1 00 01 10 11 0 1 0 1 PB0 VSAMP Timing
PB9-PB0 Bit Definition Unused channels are powered down to 0 save power (single channel mode only) Unused channels are powered up No Reset Resets all registers to the default configuration CDS pixel CDS line clamp No clamp S/H line clamp 2Vpp Full Scale 3Vpp Full Scale (recommended for better performance) RGB 3 channel color mode Red single channel mode Green single channel mode Blue single channel mode Inverted for CCD or negative going signals Non-inverted for CIS or positive going signals No buffer (DC coupled or AC coupled inputs with pixel clamp mode Buffer enabled (AC Coupled inputs for line clamp or no clamp mode Timing option #1 (see Figure 3, 4, 7 & 8 for details) Timing option #2 (see Figure 3, 4, 7 & 8 for details)
PB5 A/D Full Scale Range PB4 PB3 Color Select
PB2 Input Signal Polarity PB1 Input Buffer Enable
0 1
Table 2. Configuration Register #1 Definition (Default Configuration is 000H)
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XRD9814/9816
A2 A1 A0 Address 0 0 1 Bit Assignment PB9 Not Used PB8 Not Used PB7 Not Used PB6 Not Used PB5 Not Used PB4 PB3 PB9-PB0 Bit Definition
0 1 0 1 0 1 0 1 0 1 00
Normal This register should be set to zero for normal operation Do Not Use Normal Normal Normal Normal This register should be set to zero for normal operation This register should be set to zero for normal operation This register should be set to zero for normal operation This register should be set to zero for normal operation Do Not Use Do Not Use Do Not Use Do Not Use AVDD-0.8V (4.2V for AVDD = 5V) (See Figures 11 & 12 for VClamp Settings) AVDD-1.3V (3.7V for AVDD = 5V) AVDD-1.8V (3.2V for AVDD = 5V) AVDD-2.3V (2.7V for AVDD = 5V) Normal This register should be set to zero for normal operation Do Not Use All circuits active Low power mode (75mW, requires 5uS back to normal operation) A/D digital outputs Read back mode (A2:A1:A0 select register data)
CDS Clamp Voltage 01 (Black Level) PB2 Not Used PB1 Stand-By Mode PB0 Read Back Mode 10 11 0 1 0 1 0 1
Table 3. Configuration Register #2 Definition (Default Configuration is 000H)
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XRD9814/9816
A2 0 0 1 1 A1 1 1 0 0 A0 0 1 0 1 Function Red Gain Green Gain Blue Gain Red Offset PB9-PB8 gross adj PB7-PB0 fine adj PB9 MSB MSB MSB 00 01 10 11 00 01 10 11 00 01 10 11 0V MSB +200mV -200mV -400mV 0V MSB +200mV -200mV -400mV 0V MSB +200mV -200mV -400mV PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 LSB LSB LSB LSB
1
1
0
Green Offset PB9-PB8 gross adj PB7-PB0 fine adj
LSB
1
1
1
Blue Offset PB9-PB8 gross adj PB7-PB0 fine adj
LSB
Table 4. Gain and Offset Registers (Default Configuration is 000H)
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13
XRD9814/9816
GENERAL DESCRIPTION The XRD9814/9816 contains all of the circuitry required to create a complete 3-channel signal processor /digitizer for use in CCD/CIS imaging systems. Each channel includes a correlated double sampler (CDS), programmable gain amplifier (PGA) and channel offset adjustment. The input stage can also be configured for use with inverting/non-inverting, AC or DC coupled signals. In order to maximize flexibility, the specific operating mode is programmable through two configuration registers. In addition, the gain and offset of each channel can be independently programmed through separate gain and offset registers. Configuration register data is loaded serially through a 3-pin serial interface. Specific details for register writes are detailed below. After signal conditioning the three PGA outputs are digitized by a 14-bit/16-bit A/D converter. Writing Registers Data The XRD9814/9816 utilizes eight 10-Bit registers to store configuration, gain and offset information. Register data is written through the 3-pin serial interface consisting of SDI (serial data input), SCLK (serial shift clock) and LOAD (positive edge write enable). A write consists of pulling LOAD low, shifting in 3 bits of address (MSB first) and 10 bits of data (MSB first). Data is written on the rising edge of SCLK and the last 13 bits are latched. The timing for writing to registers is shown in Figure 17 and 18. When INSEL=0, SCLK, SDI, and LOAD pins are active for serial programming. When INSEL=1, SCLK and SDI pins are inactive, and the serial programming is done through I/O pins DB12/ DB14 and DB13/DB15 while LOAD pin is low. Configuration Register #1 The bit assignment and definition for this register is detailed in the Configuration Register #1 Definition Table (Table 2). The primary purpose of this register is to configure the analog input blocks for CCD or S/H operation. Clamp Mode The clamp mode setting determines the conditions when the internal clamp is enabled (see Table 5). The pixel and CCD line-clamp modes are used to DCrestore AC coupled CCD input signals to the PGA common-mode input voltage while using correlated double sampling. S/H line mode should be used to DCrestore AC coupled inputs which do not utilize correlated double sampling and have only one control input (VSAMP). No-clamp mode should be used for DC coupled S/H inputs. Pixel Mode (CCD with CDS) The input clamp is active each pixel period with a pulse-width determined by the Black- level Sampling Input (BSAMP). The position of BSAMP can be optimized to eliminate the effects of the CCD reset pulse. Since the input capacitor is recharged to the clamp voltage on each pixel, common-mode droop errors are eliminated. CCD Line Mode (CCD with CDS) The input clamp is enabled only at the beginning of the line by gating BSAMP with LCLMP. Gating with LCLMP maintains the ability to position the clamp pulse (BSAMP) away from the CCD reset for varying LCLMP position and width. Since the input capacitor is clamped only at the beginning of each line a larger input capacitor is required to satisfy the common-mode input requirements of the analog front-end. (See Coupling Capacitor Requirements.) The input buffer should be enabled in this mode (PB1=1, Register #1). S/H Line Mode (S/H with AC Coupling) The S/H Line mode clamp is used to DC-restore AC coupled inputs which do not utilize CDS. VSAMP is used to sample and hold the input signal and LCLMP performs the clamp function. This differs from the CDS line and pixel modes which use BSAMP to clamp to the reference level and VSAMP to hold the video input. The input buffer should be enabled in this mode (PB1=1, Register #1).
Rev. 1.00
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XRD9814/9816
No-Clamp Mode (S/H with DC input) Used for DC coupled inputs. AC coupled inputs must be externally clamped to the proper common-mode input voltage of the XRD9814/9816.
Note: Pixel clamp is the default clamp mode.
Clamp Mode Pixel CDS Line No Clamp S/H Line PB7 0 0 1 1 PB6 0 1 0 1 Clamp Enable
BSAMP BSAMP LCLMP Disabled LCLMP
Table 5. Clamp Enable Definition
Clamp Enable BSAMP
LCLMP PB6
PB7
Figure 2. Clamp Enable Logic
A/D Full-Scale Range This bit sets the Full-Scale Range (FSR) of the A/D converter to 2V or 3V. Use the 3V FSR for lowest noise performance. Color Select The color input corresponds to the signal input to be digitized by the A/D converter. If set to RGB (default) the A/D input is sequentially cycled through the red, green and blue channels. The green channel is synchronized on the rising edge of the first ADCCLK after the falling edge of VSAMP. If set in single-channel mode, the A/D multiplexer will not sequence and the A/D converter input will be continually connected to the channel that is selected, RED, GRN or BLU.
Signal Polarity This bit configures the analog inputs for positive or negative transitioning inputs. This is required to provide the correct signal polarity to the A/D input and to set the correct input clamp level. The default configuration is set to inverting mode (CCD input). Input Buffer Enable This bit enables the input buffer to the PGA amplifier and is required only for AC coupled inputs operating in CDS line or S/H line clamp modes. Since this input buffer reduces the input voltage range its use is not recommended under DC or pixel-mode operation. The input buffer is disabled in the default configuration.
Rev. 1.00
15
XRD9814/9816
VSAMP Timing This allows the user to select one of two VSAMP timing controls. Timing Option #2 allows the rising edge of VSAMP to occur approximately one-half ADCCLK earlier than Option #1. This does not affect internal timing and is provided only to allow additional flexibility in the external timing control. Timing Option #2 is available only in the 3-channel mode of operation (See timing diagrams Figure 3 and Figure 4). Configuration Register #2 The bit assignment and definition for this register is detailed in the Configuration Register #2 Definition Table. A diagnostic read-back mode allows gain, offset and configuration data to be output as the 8 or 10 MSBs on the digital output bus depending on the selection of OUTSEL (see Reading Register Data session for details). Additional bits are used to enable a low-power stand-by state and manufacturing test mode. Digital Reset Setting this bit to one resets all registers to all zeros. Test Mode This is a reserved bit for testing and must be set to 0 in all writes to Configuration Register #2. Stand-By Mode Setting this bit to one forces the circuit into a low-power standby mode. Configuration, offset and gain registers remain unchanged in stand-by mode. Pull OEB High to set DB<15:0> to high impedance during stand-by mode. Read Back Mode This is a special diagnostic mode which can aid in the debugging of new system designs. Setting this bit to 1 allows all configuration, gain and offset register contents to be output on the data output bus (explained below). (OUTSEL = 1) In nibble mode, the output bus is limited to 8-bits. Therefore, in read-back mode, the 8 MSBs are valid when ADCCLK is high, and the 2 LSBs are valid when ADCCLK is low. Configuring and exiting the read-back mode is done in the same manner of OUTSEL = 0.
Important: The entire byte of register #2 is re-written when exiting the readback mode. If any bits of configuration register #2 were programmed prior to entering the readback mode, they must be re-programmed when exiting read-back. See Figure 19 for read-back timing.
Reading Register Data In order to enter read-back mode, set configuration register #2, PB0 to 1. Follow the write timing in Figures 17 and 18. In order to read a specific register, shift in 3-bits of register address data (MSB first), followed by 10 dummy data bits. In the case of reading back configuration register #2, PB0 has to stay 1 and cannot be a dummy.
Read-Back Registers and Address
Address Data Register Cfig1 Cfig2 Red Gain Grn Gain Blu Gain Red Offset Grn Offset Blu Offset
001 XXXXXXXXXX 001 XXXXXXXXX1 010 XXXXXXXXXX 011 XXXXXXXXXX 100 XXXXXXXXXX 101 XXXXXXXXXX 110 XXXXXXXXXX 111 XXXXXXXXXX
In order to exit read-back mode perform a write to configuration register 2, PB0=0. (OUTSEL = 0) In read-back mode the A/D output is bypassed and internal register data is output to the 10 most significant bits of the data output bus. The remaining LSB bits should be ignored. Register data will be valid after the load pin goes high.
PGA Gain Settings The gain for each color input is individually programmable from 1 to 10 in 1024 linear steps.
Rev. 1.00
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XRD9814/9816
Code PGA Gain = 9. 0 + 1 1024
The fine offset correction for each channel is programmable from -300mV to +300mV.
where Code represents the binary contents of the 10bit gain setting register. Channel Offset Adjustment The gross offset correction for each channel is progammable from -400mV to +200mV. It is adjusted by toggling PB9 and PB8 of Offset Registers (Table 4).
Fine Channel Offset = PB 7
( Code ) 128 300mV
PB7=1 equals -1 PB7=0 equals +1 Code = (PB6:PB0) of the 10-bit offset register.
10-Bit Differential Input Offset Block CDS PGA
XRD9814/16
Vout 3:1 MUX 14-Bit
ADC
Programmable Serial Port
8-Bit
8-Bit Offset DAC Fine Adjust
2-Bit Offset Variable Capacitive Divider Gross Adjust
2-Bit
Block Diagram of the Fine and Gross Offset Adjustment DAC
Theory of Operation Rev. 1.00
17
XRD9814/9816
(Correlated Double Sampling) Correlated double sampling is a technique used to level shift and acquire CCD output signals whose information is equal to the difference between consecutive reference (black) and signal (video) samples. The CDS process consists of three steps: 1) Sampling and holding the reference black level. 2) Sampling the video level. 3) Subtracting the two samples to extract the video information. Once the video information has been extracted it can be processed further through amplification and/or offset adjustment. Since system noise is also stored and subtracted during the CDS process, signals with bandwidths less than half the sampling frequency will be substantially attenuated. In order to reject higher frequency power supply noise which is not attenuated near the sampling frequency the XRD9814/9816 utilizes a fully differential input structure. Since the CDS process uses AC coupled inputs the coupling capacitor must be charged to the commonmode range of the analog front-end. This can be accomplished by clamping the coupling capacitor to the internal clamp voltage when the CCD is at a reference level. This clamp may occur during each pixel (Pixel Clamp), or at the beginning of each line (CDS Line Clamp). If CDS Line Clamp mode is used the input buffer (configuration register #1, PB1) must be enabled to eliminate the effects of input bias current. If Pixel mode is selected the input buffer is not required or recommended. 3-Channel CDS Mode This mode allows simultaneous CDS of the red, green and blue inputs . Black-level sampling occurs on each pixel and is equal to the width of the BSAMP sampling input. The black level is held on the falling edge of BSAMP and the PGA will immediately begin to track the signal input until the falling edge of VSAMP. Two VSAMP timing modes are supported to allow additional flexibility in the VSAMP pulse width (see timing diagrams). At the end of the video sampling phase the difference between the reference and video levels is inverted, amplified and offset depending on the contents of the PGA gain and offset registers. The RGB channels are then sequentially converted by a high speed A/D converter. A/D converter data appears on the data output bus after 7 ADCCLK cycles. The green channel is synchronized on the rising edge of the first ADCCLK after the falling edge of VSAMP. The power-up default mode is for CDS sampling a CCD input (Pixel Clamp, Inverting Input, No Input Buffer). 1-Channel CDS Mode The 1-Channel CDS mode allows high-speed acquisition and processing of a single channel. The timing, clamp and buffer configurations are similar to the 3channel mode described previously. To select a single channel input the color bits of configuration register 1 must be set to the appropriate value. The A/D input will begin to track the selected color input on the next positive edge of ADCCLK. If the configuration is toggled from single color to 3-channel mode RGB scanning will not occur until the circuit is resynchronized on the falling edge of VSAMP.
Rev. 1.00
18
XRD9814/9816
3-Channel CIS/Sample and Hold Mode The XRD9814/9816 also supports operation for Contact Image Sensor (CIS) and S/H applications. The green channel is synchronized on the rising edge of the first ADCCLK after the falling edge of VSAMP. For DC coupled inputs the reference clamp and input buffer should be disabled and input polarity should be set to 1 (non-inverting). In this mode of operation the BSAMP input is connected to DGND and input sampling occurs on the falling edge of VSAMP. When using AC coupled inputs the coupling capacitor must be clamped to the required common-mode input voltage when the signal source output is at a reference level. This can be accomplished by enabling the S/H Line clamp mode in configuration register 1 and clamping the input capacitor to the internal clamp voltage at the beginning of each line via the LCLMP input. The required width of the LCLMP signal is dependent on the value of the coupling capacitor, XRD9814/9816 clamp resistance, source output resistance and desired accuracy. This is explained further in Coupling Capacitor Requirements. If AC coupling is used the input buffer (configuration register 1) must be enabled to eliminate input-bias current errors inherent to the sampling process. The input buffer is not required or recommended in DC coupled applications. 1-Channel CIS/ Sample and Hold Mode The 1-channel CIS S/H mode allows high-speed acquisition and processing of a single channel. The timing, clamp and buffer configurations are similar to the 3-channel mode with the exception that VSAMP timing option #2 is not supported. To select a single channel input the color bits of configuration register 1 must be set to the appropriate value. The A/D input will begin to track the selected color input on the next positive edge of ADCCLK. If the configuration is toggled from single color to 3-channel mode, RGB scanning will not occur until the circuit is resynchronized. Power Supplies and Digital I/O The XRD9814/9816 utilizes separate analog and digital power supplies. All digital I/O pins are 3V/5V compatible and allow easy interfacing to external digital ASICs. For single supply systems the analog and digital supply pins can be separately connected and bypassed to reduce noise coupling from digital to analog circuits. Coupling Capacitor Requirements The size of the external coupling capacitors depends on a number of items including the clamp mode, pixel rate, channel gain, black-level variation and system accuracy requirements. The major limitation for each clamp mode is shown below:
CDS Mode Pixel Clamp (Buffer Disabled) Black level pixel-pixel variation Initial charging Line Clamp (Buffer Enabled) Initial charging Capacitor droop (common-mode range) Capacitor droop range) (accuracy error) Initial charging S/H Mode Not Applicable
Table 5. Coupling Capacitor Limitation
Rev. 1.00
19
XRD9814/9816
Maximum Capacitance (CDS Pixel Mode) Assuming that Vr=5V, Vc=4V, V=12.5uV, Rc=100, Rs=50, tpwb=65ns and N=10 the maximum allowable input capacitor is equal to 384pF. In this case the input capacitance is limited by pixel-pixel changes in the black level (first calculation). Minimum Capacitance (CDS Pixel Mode) The minimum coupling capacitance is limited by parasitic effects including pin and board capacitance. A minimum value of 68pF is recommended. Maximum Capacitance (CDS Line Mode) Since the coupling capacitor is charged only at the beginning of each line and not clamped at each pixel, the pixel-pixel variation in the black level has no effect on the capacitor size. The maximum size will be limited by the number of clamp pulses, clamp pulse-width and number of lines allowed to charge to a given accuracy.
Limitation #1
Since the black level is clamped during each pixel period the input bias current contributes an insignificant amount of droop during one pixel period. However, pixel-pixel variations in the black level may appear as errors . For a worst case gain of -10, 2V A/D FSR and 14-bit accuracy, one lsb of error corresponds to 12.5uV input-referred. Assuming 1mV of pixel-pixel variation in the black level, the maximumcoupling capacitor can be determined as a function of the clamping period and internal clamp resistance.
C max =
tpwb
(Rc + Rs ) ln
1 mV 12.5 V
where tpwb=clamp pulse width (BSAMP) Rc=Clamp resistance Rs=Signal source-resistance
C max =
For typical values of tpwb=65ns, Rc=100, Rs=50, CMAX 100pF.
N L tpwb Vr - Vc ( Rc + Rs ) ln V
clamp pulse width (BSAMP) number of pixels allowed to settle clamp resistance signal source-resistance black level XRD9814/9816 clamp voltage error voltage
Limitation #2
The maximum input capacitance may also be limited by the time allowed to charge the input capacitor to the difference between the black level and clamp levels. The capacitor value can be related to the number of clamp pulses allowed before the capacitor voltage settles to within the desired accuracy.
where tpwb N Rc Rs Vr Vc V
= = = = = = =
C max =
tpwb N Vr - Vc (Rc + Rs ) ln V
Assuming that Vr=5V, Vc=4V, Ve=12.5uV, Rc=100, Rs=500, tpwb=65ns and N=10, the maximum allowable input capacitor is equal to 767pF. If it is desired to settle within one line (L=1) for a given capacitor value, the number of clamp pulses or the clamp pulse-width must be increased using the above equation.
where tpwb N Rc Rs Vr Vc V
= = = = = = =
clamp pulse width (BSAMP) number of pixels allowed to settle clamp resistance signal source-resistance black level XRD9814/9816 clamp voltage error voltage
Rev. 1.00
20
XRD9814/9816
Minimum Capacitance (CDS Line Mode) In general, the minimum value coupling capacitance is limited by the amount of droop which can occur before the input voltage range of the input amplifier is exceeded. The input capacitor droop is related to the input bias current by: Maximum Capacitance (S/H Line Mode) The maximum capacitance is determined by the amount of time allowed to charge the coupling capacitor. In order to minimize the charging time, the maximum capacitor can be set to the minimum value as previously calculated. In this case the time required to charge the capacitor is:
Vdroop =
Ibias n T C
t = ( Rs + Rc ) C min ln
where t Rc Rs Vr Vc V Cmin = = = = = = =
where Ibias = input bias current n = number of pixels per line T = pixel period If the minimum input voltage is allowed to equal the 0V input voltage of the XRD9814/9816, the maximum allowable droop will be equal to the clamp level minus the difference between the black and video levels. For example, if Vc=4V, and the CCD video output is -2V relative to the black level the maximum allowable droop is equal to 2V. Using the previous equation and assuming T=500ns, n=3000
Vr - Vc V
clamp pulse - width ( SYNCH ) clamp resistance signal source - resistance input reference level XRD9814/9816 clamp voltage error voltage coupling capacitor
Assuming that Vr=.5 Vc=0V, V=12.5uV, Rc=100, Rs=500 and C=1.2uF, the minimum clamp period is equal to 1.9mS.
C min =
10 nA 3000 500 ns 2V
= 7.5pF
Note: These are the absolute minimum capacitor requirements. As stated for pixel-mode, a minimum value of 68pF is recommended.
Minimum Capacitance (S/H Line Mode) Unlike Line or Pixel CDS modes voltage droop across a line appears as an absolute error and is the dominant factor in determining the minimum coupling capacitor size.
C min =
Ibias n T V
where Ibias=input bias current n=number of pixels per line Assuming n=3000, T=500nS, I=10nA and Ve=12.5uV, the minimum required capacitor is 1.2uF.
Rev. 1.00
21
XRD9814/9816
X
CCDIN tap tcp3 taclk taclk
X
ADCCLK tvfcr BSAMP tvrcr(2) tvrcf(1) tpwb
VSAMP tbvf tpwv tstl tcr3 tvbf
Clamp (Internal to XRD9814/XRD9816)
Notes: (1) VSAMP Timing Option #1 uses tvrcf (tvrcr is not required) (2) VSAMP Timing Option #2 uses tvrcr (tvrcf is not required) VSAMP Timing Option #2 only available in 3-Channel Operation
Figure 3. 3-Channel CDS Mode - Pixel Clamp
Configuration Register #1:
Pixel Clamp (PB7=0, PB6=0) RGB (PB4=0, PB3=0) Inverted Polarity (PB2=0) Input Buffer Disabled (PB1=0)
Rev. 1.00
22
XRD9814/9816
CCDIN
tap
LCLMP tcp3 taclk taclk
ADCCLK
tvfcr BSAMP tvrcr(2) tpwb VSAMP tbvf tpwv tstl tcr3 Clamp (Internal to XRD9814/XRD9816) tvrcf(1) tvbf
Notes: (1) VSAMP Timing Option #1 uses tvrcf (tvrcr is not required) (2) VSAMP Timing Option #2 uses tvrcr (tvrcf is not required) VSAMP Timing Option #2 only available in 3-Channel Operation
Figure 4. 3-Channel CDS Mode - Line Clamp
Configuration Register #1: CDS Line (PB7=0, PB6=1) RGB (PB4=0, PB3=0) Inverted Polarity (PB2=0) Input Buffer Enabled (PB1=1)
Rev. 1.00
23
XRD9814/9816
tap
CCDIN taclk
tcp1 taclk
ADCCLK
tstl BSAMP
tvfcr
tbfcr
tpwb
VSAMP tcr1 tpwv tvbf tbvf
Clamp (Internal to XRD9814/XRD9816)
Figure 5. 1-Channel CDS Mode - Pixel Clamp
Configuration Register #1: Pixel Clamp (PB7=0, PB6=0) Single Channel (PB4, PB3-RED 01, GRN 10, BLU 11) Inverted Polarity (PB2=0) Input Buffer Disabled (PB1=0)
Rev. 1.00
24
XRD9814/9816
tap
CCDIN
LCLMP taclk
tcp1 taclk
ADCCLK
tstl BSAMP
tvfcr
tbfcr
tpwb
VSAMP tcr1 tpwv tvbf tbvf
Clamp (Internal to XRD9814/XRD9816)
Notes: (1) Only VSAMP timing option #1 is supported in 1-channel mode
Figure 6. 1-Channel CDS Mode - Line Clamp
Configuration Register #1: CDS Line Clamp (PB7=0, PB6=1) Single Channel (PB4, PB3-RED 01, GRN 10, BLU 11) Inverted Polarity (PB2=0) Input Buffer Enabled (PB1=1)
Rev. 1.00
25
XRD9814/9816
tap
CIS
LCLMP tcp3 taclk taclk
tvfcr
ADCCLK tvrcf(1) VSAMP tstl tcr3 tpwv tvrcr(2)
Clamp (Internal to XRD9814/XRD9816)
Figure 7. 3-Channel S/H Mode - Line Clamp (AC Coupled)
Configuration Register #1: S/H Line Clamp (PB7=1, PB6=1) RGB (PB4=0, PB3=0) Non-Inverted Polarity (PB2=1) Input Buffer Enabled (PB1=1)
Rev. 1.00
26
XRD9814/9816
tap
CIS tcp3 taclk taclk tvfcr
ADCCLK tvrcf(1) VSAMP tstl tcr3 tpwv tvrcr(2)
Clamp (Internal to XRD9814/XRD9816)
Notes: (1) VSAMP Timing option #1 uses tvrcf (tvrcr is not required) (2) VSAMP Timing option #2 uses tvrcr (tvrcf is not required)
Figure 8. 3-Channel S/H Mode - No Clamp (DC Coupled)
Configuration Register #1: S/H No Clamp (PB7=1, PB6=0) RGB (PB4=0, PB3=0) Non-Inverted Polarity (PB2=1) Input Buffer Disabled (PB1=0)
Rev. 1.00
27
XRD9814/9816
tap
CIS
LCLMP tcp1 taclk taclk
ADCCLK tstl VSAMP tvrcf(1) tpwv tcr1 tvfcr
Clamp (Internal to XRD9814/XRD9816)
Figure 9. 1-Channel S/H Mode - Line Clamp (AC Coupled)
Configuration Register #1: S/H Line Clamp (PB7=1, PB6=1) Single Channel (PB4, PB3-RED 01, GRN 10, BLU 11) Non-Inverted Polarity (PB2=1) Input Buffer Enabled (PB1=1)
Rev. 1.00
28
XRD9814/9816
tap
CIS tcp1 taclk taclk
ADCCLK tstl VSAMP tvrcf(1) tpwv tcr1 tvfcr
Clamp (Internal to XRD9814/XRD9816)
Notes: (1) Only VSAMP timing option #1 is supported in 1-channel mode
Figure 10. 1-Channel S/H Mode - No Clamp (DC Coupled)
Configuration Register #1: S/H No Clamp (PB7=1, PB6=0) Single Channel (PB4, PB3-RED 01, GRN 10, BLU 11) Non-Inverted Polarity (PB2=1) Input Buffer Disabled (PB1=0)
Rev. 1.00
29
XRD9814/9816
5.0 V 4.7 V VCLAMP=4.2 V
0.5V
2.0V
Reset
Black Pixel
Video Pixel
Ground Typical Operation, VCLAMP = 4.2V, (PB4 = 0, PB3 = 0) VRESET = 0.5V, VVIDEO = 2.0V = FSR of XRD9814/9816
Figure 11. VCLAMP Setting Example 1
5.2 V 5.0 V 2.0V
VCLAMP=3.2 V
3.0V
Reset Ground
Black Pixel
Video Pixel
Marginal Operation, VCLAMP = 3.2V, (PB4 = 1, PB3 = 0) VRESET = 2.0V, VVIDEO = 3.0V = FSR of XRD9814/9816 Notes (3) Input signal does not exceed V DD + 0.3V (Reset) Notes (4) Input signal does not go below 0V (Video pixel)
Figure 12. VCLAMP Setting Example 2
Rev. 1.00
30
XRD9814/9816
Pixel (n) CCDOUT (Parallel RGB)
Pixel (n+1)
Pixel (n+2)
Pixel (n+3)
Pixel (n+4)
7 ADCCLK Latency ADCCLK
BSAMP ADC Samples Green VSAMP Red Pixel (n+1) Red Pixel (n) Grn Pixel (n+1) Grn Pixel (n+1)
Grn Pixel (n)
Figure 13. 3-Channel CDS Pixel Clamp Synchronization and ADC Latency Timing
Pixel (n) CCDOUT (Green Input)
Pixel (n+1)
Pixel (n+2)
Pixel (n+3)
Pixel (n+4)
Pixel (n+5) Pixel (n+6) Pixel (n+7)
Pixel (n+8)
7 ADCCLK Latency
ADCCLK
BSAMP
VSAMP
Grn Pixel (n-3)
Grn Pixel (n-2)
Grn Pixel (n-1)
Blu Pixel (n) Grn Pixel (n)
Figure 14. 1-Channel CDS Pixel Clamp Synchronization and ADC Latency Timing
Rev. 1.00
31
XRD9814/9816
Pixel (n) CISOUT (Parallel RGB) Pixel (n+1) Pixel (n+2) Pixel (n+3) Pixel (n+4)
7 ADCCLK Latency ADCCLK ADC Samples Green VSAMP Red Pixel (n+1) Red Pixel (n) Grn Pixel (n+1) Grn Pixel (n+1)
Grn Pixel (n)
Figure 15. 3-Channel S/H Synchronization and ADC Latency Timing
Pixel (n) CISOUT (Green Input)
Pixel (n+1)
Pixel (n+2)
Pixel (n+3)
Pixel (n+4)
Pixel (n+5) Pixel (n+6) Pixel (n+7)
Pixel (n+8)
7 ADCCLK Latency
ADCCLK
VSAMP
Grn Pixel (n-3)
Grn Pixel (n-2)
Grn Pixel (n-1)
Blu Pixel (n) Grn Pixel (n)
Figure 16. 1-Channel S/H Synchronization and ADC Latency Timing
Rev. 1.00
32
XRD9814/9816
13 Data Bits
SCLK (Pin 41) tds SDI (Pin 40) tlcs tlch LOAD (Pin 39) tplw A2 A1 A0 PB9 PB8 tdh PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Rising edge loads last 13 Data bits
Figure 17. Write Timing (INSEL = 0)
SCLK/ DB12/DB14 (Pin 45) tds SDI/ DB13/DB15 (Pin 44) A2 A1 tlcs tlch LOAD (Pin 39) A0 PB9 PB8
13 Data Bits
tdh PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
tlch tplw
Rising edge loads last 13 Data bits
Figure 18. Write Timing (INSEL = 1)
Rev. 1.00
33
XRD9814/9816
XRD9814/9816 Read Back Timing
LOAD
SCLK
Enables Read-back
Disables Read-back
SDI Output (DBx)
001XXXXXXXXX1
000XXXXXXXXXX
001XXXXXXXXX0
Cfig2 ADC Output Data Reg data Not Valid
Cfig1 Reg data
Not Valid
ADC Output Data
Write to Cfig2, bit0 to enable readback & Address Cfig2 for register read-back
Read-back Cfig2 data
Address Cfig1 for register read-back
Read-back Cfig1 data
Write to Cfig2 bit0 to enable ADC output data & disable read-back mode
This step can be repeated for all registers before exiting to normal mode
Note: If any bits of Cfig2 were programmed prior to readback mode, they must be re-programmed when exiting read-back
Figure 19. XRD9814/9816 Read-Back Timing
Rev. 1.00
34
XRD9814/9816
OEB
N ADCCLK
N+1
tod DB13:0/ DB15:0 TRI-STATE tlz DB13/15:0 (N-6)
thz TRI-STATE
DB13/15:DB0 (N-7)
LOAD
LOAD = HI
Figure 20. ADC Digital Output Timing (OUTSEL = 0)
OEB
N ADCCLK tod tod DB13:0/ DB15:0 TRI-STATE tlz High Bits LOAD = HI N-8 (LSB 6/8-BITS) N-7 (MSB 8-BITS)
N+1
thz N-7 (LSB 6/8-BITS) Low Bits N-6 (MSB 8-BITS) TRI-STATE
LOAD
Figure 21. ADC Digital Output Timing (OUTSEL = 1)
Rev. 1.00
35
XRD9814/9816
tap
CCD tstl N-1 VSAMP N N+1 N+2 N+3
ADCCLK 1 ADCOUT 2 3 4 5 Non Valid Data 6 7 8 9 10 Dummy N-1 7 ADCCLK Latency 11 GRN N-1 12 BLU N-1 13 RED N 14 GRN N BLU N
Figure 22. XRD9814/XRD9816 Pipeline Latency
ADCCLK/SYNCHRONIZATION EVENTS
1 2 3 4 5 6 7 8 9 10 11
Necessary / No Sampling Events Occur Beginning of Synchronization / Samples Green (N-1) / Converts Unkown Dummy Value Samples Blue (N-1) / Converts Green (N-1) Samples Red (N) / Converts Blue (N-1) Synchronization / Samples Green (N) / Converts Red (N) Samples Blue (N) / Converts Green (N) Samples Red (N+1) / Converts Blue (N) Synchronization / Samples Green (N+1) / Converts Red (N+1) Dummy Pixel (N-1) Valid Generated From ADCCLK #2 GRN Pixel (N-1) Valid Generated From ADCCLK #3 BLU Pixel (N-1) Valid Generated From ADCCLK #4 RED Pixel (N) Valid Generated From ADCCLK #5 GRN Pixel (N) Valid Generated From ADCCLK #6 BLU Pixel (N) Valid Generated From ADCCLK #7
12 13 14
Note: Green Channel is Synchronized on the First Rising Edge of ADCCLK After the Falling Edge of VSAMP
Rev. 1.00
36
XRD9814/9816
Application Notes
Avdd c1 c2 Dvdd c3 c4 c1=c3=0.1uF c2=c4=0.01uF A v d d D v d d
Data 14/16 - 8 Bit Databus (ASIC)
No Connect No Connect C C D / C I S
Red(+) Red(-) Grn(+) Grn(-)
Ext Serial Load Control Signals
XRD9814/XRD9816
No Connect No Connect
Blu(+) Blu(-)
c r e f
c a p p
c a p n
A g n d
D g n d
0.1uF 2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
Figure 23. Single Channel DC-Coupled Mode
Avdd c1 c2
2.2uF
Dvdd c3 c4 c1=c3=0.1uF c2=c4=0.01uF
C C D / C I S
100pF
No Connect No Connect
Red(+) Red(-) Grn(+) Grn(-)
A v d d
D v d d
Data 14/16- 8 Bit Databus (ASIC)
Ext Serial Load Control Signals
XRD9814/XRD9816
100pF No Connect No Connect Blu(+) Blu(-)
c r e f
c a p p
c a p n
A g n d
D g n d
0.1uF 2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
Figure 24. Single Channel AC-Coupled Mode
Rev. 1.00
37
2.2uF
XRD9814/9816
Avdd c1 c2 Dvdd c3 c4 c1=c3=0.1uF c2=c4=0.01uF A v d d D v d d
Data 14/16-8 Bit Databus (ASIC) Ext Serial Load Control Signals
C C D / C I S
Red(+) Red(-) Grn(+) Grn(-)
XRD9814/XRD9816
Blu(+) Blu(-)
c r e f
c a p p
c a p n
A g n d
D g n d
0.1uF 2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
Figure 25. Triple Channel DC-Coupled Mode
Avdd c1 c2
2.2uF
Dvdd c3 c4 c1=c3=0.1uF c2=c4=0.01uF
100pF 100pF 100pF 100pF 100pF 100pF Red(+) Red(-) Grn(+) Grn(-) A v d d
C C D / C I S
D v d d
Data 14/16-8 Bit Databus (ASIC) Ext Serial Load Control Signals
XRD9814/XRD9816
Blu(+) Blu(-)
c r e f
c a p p
c a p n
A g n d
D g n d
0.1uF 2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
Figure 26. Triple Channel AC-Coupled Mode
Rev. 1.00
38
2.2uF
XRD9814/9816
INSEL/OUTSEL Data Output Format There are two control signals for setting the output data format and the serial load control. INSEL is used to select the mode for programming the serial port. To use the external pins sdi, sclk and load, INSEL must be low (Figure 17). When INSEL is set to high, DB13/ sdi and DB12/sclk become inputs through the bidirectional output bus to load the internal control registers (Figure 18). The load pin is still used to latch the data. This helps to reduce the pin count requirements for the ASIC that drives the XRD9814/9816. OUTSEL is used to select the output data format of the XRD9814/9816. The XRD9814/9816 supports 14/16bit parallel and 8-bit nibble output modes. When OUTSEL is low, the output bus is standard 14/16-bit parallel (Figure 20). To use the 8-bit nibble output mode, OUTSEL must be set high (Figure 21). In either 14/16-bit or 8-bit nibble applications, the output bus is tri-stated when the bi-directional serial load signal is pulled low.
DB13/DB15 DB12/DB14
14/16-Bit Parallel
Digital ASIC
XRD9814/ XRD9816
DB0 sdi sclk load Insel Outsel External Serial Load
Insel=0, Outsel=0
Figure 27. 14/16-Bit Output (OUTSEL=0), External Serial Load (INSEL=0)
14/16-Bit Parallel Bi-Directional Serial Load
DB13/DB15/sdi DB12/DB14/sclk
Digital ASIC
XRD9814 / XRD9816
DB0 sdi sclk load Insel Outsel No Connect No Connect Insel=1, Outsel=0
Figure 28. 14/16-Bit Output (OUTSEL=0), Bi-Directional Serial Load (INSEL=1)
Rev. 1.00
39
XRD9814/9816
DB13/DB15 DB12/DB14
8-Bit Nibble Digital ASIC
XRD9814 /
DB6/DB8
XRD9816
sdi sclk load Insel Outsel
External Serial Load
Insel=0, Outsel=1
Figure 29. 8-Bit Nibble Output (OUTSEL=1), External Serial Load (INSEL=0)
DB13/DB15/sdi DB12/DB14/sclk
8-Bit Nibble Bi-Directional Serial Load
Digital ASIC
XRD9814 /
DB6/DB8
XRD9816
sdi sclk load Insel Outsel No Connect No Connect Insel=1, Outsel=1
Figure 30. 8-Bit Nibble Output (OUTSEL=1), Bi-Directional Serial Load (INSEL=1)
Rev. 1.00
40
XRD9814/9816
XRD9814 1 Channel CIS No Clamp, AVDD = DVDD = 5V, Fs = 6MSPS, 2V Reference DNL PLOT
1.5
1
0.5
LSB
0
-0.5
-1
-1.5 10248 10675 11102 11529 11956 12383 12810 13237 13664 14091 14518 14945 15372 15799 16226 427 854 1281 1708 2135 2562 2989 3416 3843 4270 4697 5124 5551 5978 6405 6832 7259 7686 8113 8540 8967 9394 9821 0
Codes
Graph 1. XRD9814 1-Channel CIS S/H No Clamp DNL Plot
Rev. 1.00
41
XRD9814/9816
XRD9814 1-Channel CDS Pixel Clamp, AVDD = DVDD = 5V, Fs = 6MSPS, 2V Reference, DNL Plot
0.6
0.4
0.2
LSB
0
-0.2
-0.4
-0.6 0 426 852 1278 1704 2130 2556 2982 3408 3834 4260 4686 5112 5538 5964 6390 6816 7242 7668 8094 8520 8946 9372 9798 10224 10650 11076 11502 11928 12354 12780 13206 13632 14058 14484 14910 15336 15762 16188
Codes
Graph 2. XRD9814 1-Channel CDS Pixel Clamp DNL Plot
Rev. 1.00
42
XRD9814/9816
XRD9814 3-Channel CDS Pixel Clamp, AVDD = DVDD = 5V, Fs = 6MSPS, 2V Reference, DNL Plot
0.8
0.6
0.4
0.2
LSB
0
-0.2
-0.4
-0.6
-0.8 10224 10650 11076 11502 11928 12354 12780 13206 13632 14058 14484 14910 15336 15762 16188 426 852 1278 1704 2130 2556 2982 3408 3834 4260 4686 5112 5538 5964 6390 6816 7242 7668 8094 8520 8946 9372 9798 0
Code
Graph 3. XRD9814 3-Channel CDS Pixel Clamp DNL Plot
Rev. 1.00
43
XRD9814/9816
XRD9814 1CH DC CIS Input Referred Noise vs. Gain of 1.63 to 5 V/V ADCCLK = 1MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 3V
3
2.5
2
RMS Noise (LSB)
1.5
1
0.5
0 1.63 2.75 Gain 3.88 5
Graph 4. XRD9814 1-Channel CIS S/H No Clamp Input Referred Noise vs. Gain (1 MSPS)
Rev. 1.00
44
XRD9814/9816
XRD9814 1CH DC CIS Input Referred Noise vs. Gain of 1.63 to 5 V/V ADCCLK = 6MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 3V
4
3.5
3
2.5 RMS Noise (LSB)
2
1.5
1
0.5
0 1.63 2.75 Gain 3.88 5
Graph 5. XRD9814 1-Channel CIS S/H No Clamp Input Referred Noise vs. Gain (6 MSPS)
Rev. 1.00
45
XRD9814/9816
XRD9814 3CH CDS Input Referred Noise vs. Gain of 1.63 to 5 V/V ADCCLK = 6MSPS, AVDD = 5V, DVDD = 3V, ADC Input Range = 3Vpp
6
5
4 RMS Noise (LSB)
Input Referred Noise Red Channel 3 Input Referred Noise Green Channel Input Referred Noise Blue Channel
2
1
0 1.63 2.75 Gain 3.88 5
Graph 6. XRD9814 3-Channel CDS Pixel Clamp Input Referred Noise vs. Gain
Rev. 1.00
46
XRD9814/9816
XRD9814/9816 Gain vs. Gain Code
10
9
8
7
6 Gain red 5 green blue 4
3
2
1
0 0 63 127 191 255 319 383 447 511 Gain Code 575 639 703 767 831 895 959 1023
Graph 7. XRD9814/9816 Gain vs. Gain Code
Rev. 1.00
47
XRD9814/9816
XRD9814/9816 3CH CDS, AVDD = 5V, DVDD = 3V, Fs = 6MSPS, 3Vpp, Gain = 0.5 - 5 V/V Output Referred System Offset Vs. Gain Inputs AC Coupled to Ground with 100pF Capacitors
100
95
Output Referred System Offset (mV)
90
85 Red Channel Offset 80 Green Channel Offset Blue Channel Offset 75
70
65
60 0.50 0.78 1.06 1.34 1.63 1.91 2.19 2.47 2.75 3.03 3.31 3.59 3.88 4.16 4.44 4.72 5.00 Gain (V/V)
Graph 8. XRD9814 /9816 3-Channel CDS Pixel Clamp System Offset vs. Gain
Rev. 1.00
48
LSB -0.5 0.5 1.5 0 1 -1 0 1664 3328 4992 6656 8320 9984 11648 13312 14976 16640 18304 19968 21632 23296 24960 26624 28288 29952 Codes 31616 33280 34944 36608 38272 39936 41600 43264 44928 46592 48256 49920 51584 53248 54912 56576 58240 59904 61568 63232
Rev. 1.00
XRD9816 3-Channel CDS Pixel Clamp Mode, AVDD = DVDD = 5V, Fs = 6MSPS, 2V Reference, DNL Plot
Graph 9. XRD9816 3-Channel CDS Pixel Clamp DNL Plot
49
XRD9814/9816
XRD9814/9816
XRD9816 1CH DC CIS Input Referred Noise vs. Gain of 1.63 to 5 V/V ADCCLK = 1MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 3V
12
10
8 RMS Noise (LSB)
6
4
2
0 1.63 2.75 Gain 3.88 5
Graph 10. XRD9816 1-Channel CIS SS/H No Clamp Input Referred Noise vs. Gain (1 MSPS)
Rev. 1.00
50
XRD9814/9816
XRD9816 1CH DC CIS Input Referred Noise vs. Gain of 1.63 to 5 V/V ADCCLK = 6MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 3V
14
12
10
RMS Noise (LSB)
8
6
4
2
0 1.63 2.75 Gain 3.88 5
Graph 11. XRD9816 1-Channel CIS SS/H No Clamp Input Referred Noise vs. Gain (6 MSPS)
Rev. 1.00
51
XRD9814/9816
Rev. 1.00
52
XRD9814/9816
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1999 EXAR Corporation Datasheet December 1999 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.00
53

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